1. Technical Field
The present invention relates to an electronic circuit and an electronic device including an electronic circuit, more particularly, an electronic device that receives a UWB (Ultra Wide Band) signal.
2. Related Art
Circuits that detect an envelope of a received signal to demodulate a baseband signal have been used since a long time ago, and various kinds of the circuits have been devised. An envelope is a curve connecting peak value of a signal and can be obtained by smoothing the absolute value of the AC component. Instead of the envelope detection, there has also been a method of squaring and smoothing a signal since a long time ago, which is called “square-law detection” or the like. For example, JP-A-4-170807 describes a square-law detector circuit that obtains the square value of a signal and an amplitude detection method using the square-law detector circuit.
In a UWB communication through UWB signals, especially through IR (Impulse Radio) not using a carrier wave (hereinafter referred to as “UWB-IR” communication), there is a receiver using the envelope detection. For example, JP-A-2004-320083 or JP-A-2005-252740 describes the effectiveness of the envelope detection. In JP-A-2004-320083 or JP-A-2005-252740, a rectifier circuit and an integrator circuit are used for smoothing the absolute value of the AC component of a signal to determine the envelope. Hereinafter, an operation detecting the envelope of a modulated carrier wave (high-frequency signal that changes in amplitude with the lapse of time) is referred to as “envelope detection”. An example of using the square-law detection in a UWB-IR receiver cannot be found.
“A CMOS IMPULSE RADIO ULTRA-WIDEBAND TRANCEIVER FOR 1 Mb/s DATA COMMUNICATION AND ±2.5 cm RANGE FINDINGS” T. Terada et. al, 2005 Symposium on VLSI Circuits Digest of Technical Papers, PP. 30-33, discloses a technique for reducing the power consumption of a device by cutting off a power supply in a transmitting and receiving circuit when there is no signal because a UWB-IR signal is intermittent.
However, when attempting to reduce the power consumption of equipment by utilizing the intermittency of the signal in a UWB-IR receiver, there arises a considerable difficulty. FIG. 7 is a circuit diagram for explaining a problem in the related-art. FIG. 8 is a timing diagram for explaining the problem in the related-art.
As shown in FIG. 7, a related-art electronic circuit 7 includes a low noise amplifier (LNA) 100 that can perform switching operation and an envelope detection circuit 200.
The LNA 100 includes a cascode amplifier circuit composed of an inductor 107, a resistance 105, and NMOS transistors 103 and 101 connected in series between a power supply voltage line vdd and a ground potential line, and an inductor 108, a resistance 106, and NMOS transistors 104 and 102 connected in series between the power supply voltage line vdd and the ground potential line. The LNA 100 further includes a capacitor 109 and an inductor 110 connected in series between an input terminal In1 and the gate terminal of the NMOS transistor 101, a capacitor 112 and an inductor 113 connected in series between an input terminal In2 and the gate terminal of the NMOS transistor 102, a resistance 111 connected between a bias voltage terminal bs1 and the connecting line of the capacitor 109 and the inductor 110, and a resistance 114 connected between the bias voltage terminal bs1 and the connecting line of the capacitor 112 and the inductor 113. The gate terminals of the NMOS transistors 103 and 104 are connected to an input terminal bs0.
The LNA 100 amplifies balanced differential signals a1 and a2 input to the input terminals In1 and In2 and outputs differential signals c1 and c2 respectively from an output line 115 connected to the connecting line of the inductor 108 and the resistance 106 and from an output line 116 connected to the connecting line of the inductor 107 and the resistance 105.
The LNA 100 can control current flowing into the LNA 100 by controlling a voltage Vb applied to the input terminal bs0. That is, when the voltage Vb is set to a voltage value (L level) lower than the threshold voltage of the NMOS transistors 103 and 104, the NMOS transistors 103 and 104 are cut off. Therefore, the current flowing into the LNA 100 is zero. On the other hand, when the voltage Vb is set to a bias voltage value (H level) that is higher than the threshold voltage of the NMOS transistors 103 and 104 and at which the NMOS transistors 103 and 104 start to operate as a cascode stage, the LNA 100 starts to operate as a cascode amplifier circuit. The resistances 105 and 106 are used for stabilizing the LNA 100. Current signals amplified by the cascode stage are converted to voltages by the inductors 107 and 108 and output as differential outputs from the output lines 115 and 116 as the differential signals c1 and c2.
The envelope detection circuit 200 includes a cascode amplifier circuit composed of PMOS transistors 211 and 213 connected in series between the power supply voltage line vdd and the ground potential via a NMOS transistor 216 and PMOS transistors 212 and 214 connected in series between the power supply voltage line vdd and the ground potential via the NMOS transistor 216.
The gate terminal of the NMOS transistor 216 is connected to a bias voltage terminal bs2 and outputs a square sum signal e=c12+c22 of the differential signals c1 and c2 output from the output lines 115 and 116 of the LNA 100 from the output line 215 connected to the drain terminal of the NMOS transistor 216 and the drain terminals of the PMOS transistors 213 and 214 and an output terminal Out. The gate terminals of the PMOS transistors 213 and 214 are connected to a bias voltage terminal bs3. The gate terminal of the PMOS transistor 211 is connected to the output line 115 via a capacitor 121. The gate terminal of the PMOS transistor 212 is connected to the output line 116 via a capacitor 122. The gate terminal of the PMOS transistor 211 is connected to a bias voltage terminal bs4 via a resistance 217. The gate terminal of the PMOS transistor 212 is connected to the bias voltage terminal bs4 via a resistance 218.
When the PMOS transistors 213 and 214 are biased by a voltage applied to the bias voltage terminal bs3 and are operating in the saturated region, drain currents Id1 and Id2 respectively flowing into the PMOS transistors 211 and 212 are as follows:Id1=(½)β(Vbs4+v1−Vt)2  (1)Id2=(½)β(Vbs4+v2−Vt)2  (2)where v1 and v2 are the AC components of voltages of the differential signals c1 and c2, respectively; Vbs4 is the bias voltage applied by the bias voltage terminal bs4; Vt is the threshold voltage of the PMOS transistors 211 and 212; W is the channel width; L is the channel length; μ is the carrier mobility; C is the gate capacitance per unit area; and β=μC (W/L) is the proportional constant. The total current of Id1 and Id2 flows into a current source load as the transistor 216 and can be converted to a large voltage signal to be extracted.
When v1=v0 and v2=−v0 on the assumption that the differential signals c1 and c2 are ideal balanced signals having no in-phase component, the following equation is given.I0=Id1+Id2=β{v02+(Vbs4−Vt)2}  (3)
The PMOS transistors 213 and 214 decrease the change of drain voltage of the PMOS transistors 211 and 212 and prevent the decrease of drain current (drain current looks like decreasing in terms of equivalence) of the PMOS transistors 211 and 212 by a phenomenon called channel length modulation, thereby acting to enhance the accuracy of Equation (3).
Since (Vbs4−Vt)2 on the right side of Equation (3) is the DC component, when only the amount of change is extracted, the square value of the input signal v0 input to the envelope detection circuit 200 can be extracted. The DC component of (Vbs4−Vt)2 can be easily removed by the capacitors 121 and 122. Only the DC component that can be easily removed is left as an error term even if any bias voltage Vbs4 is selected. Therefore, the PMOS transistors 211 and 212 can be set in a region where they can stably operate.
However, when attempting to cause the LNA 100 to perform the switching operation with the voltage Vb applied to the input terminal bs0, the differential signals c1 and c2 output by the LNA 100 do not become ideal balanced signals, and a large in-phase component is mixed thereto as noise. Therefore, noise cannot be removed.
With reference to FIG. 8, the case where the LNA 100 performs switching operation will be described.
As shown in FIG. 8, differential signals a1 and a2 indicating data “1” (with pulses) are first input during time points t0 to t1. When the voltage Vb to be applied to the input terminal bs0 is changed from the L level to the H level at the time point to, a noise n0 occurs in the differential signals c1 and c2 output by the LNA 100. The noise n0 also occurs in the square sum signal e. Next, when the voltage Vb is changed from the H level to the L level for bringing the LNA 100 into a resting state during the time point t1 to a time point t2, a noise n1 occurs in the differential signals c1 and c2. The noise n1 also occurs in the square sum signal e. Next, the differential signals a1 and a2 indicating data “0” (no pulse) is input during the time point t2 to a time point t3. When the voltage Vb to be applied to the input terminal bs0 is changed from the H level to the L level at the time point t2, a noise n2 occurs in the differential signals c1 and c2 output by the LNA 100. The noise n2 also occurs in the square sum signal e.
In this manner, every time the LNA 100 performs the switching operation with the voltage Vb, the noise occurs. Therefore, the data of the differential signals a1 and a2 cannot be read correctly. That is, there is a problem that the switching operation of the LNA 100 for reducing the power consumption of the electronic circuit 7 leads to deterioration of sensitivity for signal reading.